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Interactive tool for specifying dedicated hardware accelerators
João Paulo Rebocho - Dissertation 2nd semester MIEEC
N. Paulino, "Transparent Generation of Reconfigurable Hardware at Runtime from Execution Traces," 2013.
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J. Bispo, N. Paulino, J. M. P. Cardoso, and J. C. Ferreira, "Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units," International Journal of Reconfigurable Computing, 2013.
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H. Noori, F. ehdipour, K. Murakami, K. Inoue, and M. S. Zamani, “An architecture framework for an adaptive extensible processor,” Journal of Supercomputing, vol. 45, no. 3, 2008.
J. Bispo, "Mapping Runtime-Detected Loops from Microprocessors to Reconfigurable Processing Units," 2012.
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M. LIU, "Nest-loop transformation techniques considering timing and memory optimization for embedded systems," Doctor of Philosophy in Computer Science, University of Texas, 2006.
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